Open Source VHDL Verification Methodology (OSVVM)

Open Source VHDL Verification Methodology (OSVVM) provides utility and model libraries that simplify your FPGA and ASIC verification tasks. Using these libraries you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC.

OSVVM is the #1 VHDL Verification Methodology

According to the 2018 Wilson Verification Survey, OSVVM is the:

• #1 VHDL Verification Methodology

• #1 FPGA Verification Methodology in Europe (ahead of SystemVerilog + UVM)

The OSVVM Utility Library

The OSVVM utility library offers the same capabilities as those provided by other verification languages (such as SystemVerilog and UVM). For more see: OSVVM Utility Library

The OSVVM Verification IP Library (aka Verification Components)

The OSVVM model library is a growing set of models commonly used for FPGA and ASIC verification. For information more see: Documentation Comming Soon